Mrs Univers is the stand-alone Marvelous RTL Simulator of AdvEDA’s Unified Verification Solutions, which is also part of Miss Univers. It is a blazingly fast RTL simulator with a cycle-based kernel using 2-state logic models, resulting in a 100x speed increase over traditional simulators. Mrs Univers supports the full synthesizable VHDL syntax, including multiple asynchronous clocks, tri-state signals and it warns for reading undefined values from external signals or memory locations as well.